1. Field of the Invention
The present invention generally relates to the formation of integrated circuits, and, more particularly, to a process flow for forming a contact layer including bumps, wherein the contact layer is configured to provide contact areas for directly attaching an appropriately formed package or carrier substrate to a die carrying one or more integrated circuits.
2. Description of the Related Art
In manufacturing integrated circuits, it is usually necessary to package a chip and provide leads and terminals for connecting the chip circuitry with the periphery. In some packaging techniques, chips, chip packages or other appropriate units may be connected by means of solder balls, formed from so-called solder bumps, that are formed on a corresponding layer, which will be referred to herein as a contact layer, of at least one of the units, for instance on a dielectric passivation layer of the microelectronic chip. In order to connect the microelectronic chip with the corresponding carrier, the surfaces of two respective units to be connected, i.e., the microelectronic chip comprising, for instance, a plurality of integrated circuits, and a corresponding package having formed thereon adequate pad arrangements to electrically connect the two units after reflowing the solder bumps provided on at least one of the units, for instance on the microelectronic chip. In other techniques, solder bumps may have to be formed that are to be connected to corresponding wires, or the solder bumps may be brought into contact with corresponding pad areas of another substrate acting as a heat sink. Consequently, it may be necessary to form a large number of solder bumps that may be distributed over the entire chip area, thereby providing, for example, the I/O capability required for modern microelectronic chips that usually include complex circuitry, such as microprocessors, storage circuits and the like, and/or include a plurality of integrated circuits forming a complete complex circuit system.
In order to provide hundreds or thousands of mechanically well-fastened solder bumps on corresponding pads, the attachment procedure of the solder bumps requires a careful design since the entire device may be rendered useless upon failure of only one of the solder bumps. For this reason, one or more carefully chosen layers are generally placed between the solder bumps and the underlying substrate or wafer including the pad arrangement. In addition to the important role these interfacial layers, herein also referred to as underbump metallization layer, may play in endowing a sufficient mechanical adhesion of the solder bump to the underlying pad and the surrounding passivation material, the underbump metallization has to meet further requirements with respect to diffusion characteristics and current conductivity. Regarding the former issue, the underbump metallization layer has to provide an adequate diffusion barrier to prevent the solder material, frequently a mixture of lead (Pb) and tin (Sn), from attacking the chip's underlying metallization layers and thereby destroying or negatively affecting their functionality. Moreover, migration of solder material, such as lead, to other sensitive device areas, for instance into the dielectric, where a radioactive decay in lead may also significantly affect the device performance, has to be effectively suppressed by the underbump metallization. Regarding current conductivity, the underbump metallization, which serves as an interconnect between the solder bump and the underlying metallization layer of the chip, has to exhibit a thickness and a specific resistance that does not inappropriately increase the overall resistance of the metallization pad/solder bump system. In addition, the underbump metallization will serve as a current distribution layer during electroplating of the solder bump material. Electroplating is presently the preferred deposition technique, since physical vapor deposition of solder bump material, which is also used in the art, requires a complex mask technology in order to avoid any misalignments due to thermal expansion of the mask while it is contacted by the hot metal vapors. Moreover, it is extremely difficult to remove the metal mask after completion of the deposition process without damaging the solder pads, particularly when large wafers are processed or the pitch between adjacent solder pads decreases.
Although a mask is also used in the electroplating deposition method, this technique differs from the evaporation method in that the mask is created using photolithography to thereby avoid the above-identified problems caused by physical vapor deposition techniques. However, electroplating requires a continuous and uniform current distribution layer adhered to the substrate that is mainly insulative, except for the pads on which the solder bumps have to be formed. Thus, the underbump metallization also has to meet strictly set constraints with respect to a uniform current distribution as any non-uniformities during the plating process may affect the final configuration of the solder bumps and, after reflowing the solder bumps, of the resulting solder balls in terms of, for instance, height non-uniformities, which may in turn translate into fluctuations of the finally obtained electric connections and the mechanical integrity thereof.
After the formation of the solder bumps, the underbump metallization has to be patterned so as to electrically insulate the individual solder bumps from each other. The resulting islands of underbump metallization, typically obtained by highly complex isotropic etch processes including wet chemical and/or electrochemical etch procedures with complex chemistry, also significantly determine the functionality and configuration of the solder balls, since the etch chemistry may result in under-etching of the solder bumps which act as a mask during the wet chemical etch process. Consequently, a varying degree of under-etch may result in a varying size of the resulting underbump metallization islands associated with each solder bump, thereby significantly affecting the configuration of the solder ball after reflow as the highly wettable underbump metallization substantially determines the flow behavior of the solder material and thus the finally obtained size and hence the height of the solder ball. Moreover, the wet chemical etch process for patterning one or more sub-layers of the underbump metallization, such as a titanium tungsten (TiW) layer, which is frequently used as the first layer formed on the dielectric material due to the superior characteristics in view of barrier and adhesion, may exhibit a bump pattern dependent etch rate. That is, the etch rate may depend on the bump layout within each die and the distances in the X-direction and the Y-direction between individual dies on the substrate. Thus, the pattern dependent etch rate may impose severe constraints with respect to the actually usable bump layout, thereby possibly restricting I/O capabilities and/or heat dissipation of the die with respect to the actually available die area.
Furthermore, some wet chemical etch processes tend to significantly interact with the bump material, wherein the bump material may be removed and/or a chemical reaction may convert bump material into a non-desired compound. Hence, after the wet chemical etch process, during the wet chemical process or during a subsequent cleaning process for removing any non-desired compound, a significant amount of the bump material may be lost, which may contribute to increased production cost, especially when expensive solder materials are used, such as tin/lead with a low alpha decay rate.
Moreover, due to the complexity of the wet etch chemistry and the etch recipes, sophisticated endpoint detection procedures may be necessary during the patterning of the underbump metallization, thereby additionally contributing to process complexity. In some cases, the provision of the chemistry and of required additives for the wet chemical processes, as well as the disposal of the wet chemical byproducts, may also add significant costs to the overall patterning process, wherein maintenance and floor space for dedicated process tools may also represent an important cost factor.
In view of the situation described above, there is a need for an improved technique for forming a contact layer including solder bumps, wherein one or more of the problems identified above are avoided or the effects thereof are at least significantly reduced.